.
Corresponding messages are also recorded in the Test Log.
Note: PC Communications Version 2.10 was released on March 2004 and is available for download free of charge.
This is a maintenance upgrade incorporating several minor improvements. In particular, we have added an automatic SPD Verify function to the Production Mode, which halts the test if the SPD programming fails.
Note: Most of our R&D efforts are concentrated on the new RAMCHECK LX. Please contact us for special trade-in options.
Added support for more SUN 200-pin modules. Improved PC-100 determination for the Sync DIMMCHECK 144 (for 144-pin S.O. DIMM modules).
Added support for a COMPAQ uniquely structured 168-pin SDRAM modules.
Added support for some uniquely structured 168-pin modules. Added enhancements for the PC Communications program.
This version includes an additional 100MHz CAS LATENCY 2 test at
the end of BASIC TEST with a reporting message at the lower right
cornter of the display showing CL2=.
Corresponding messages are also recorded in the Test Log.
Added support for several new large SDRAM chips.
Version 1.49 improves the testing at 133MHz and provides several test algorithm enhancements. We have also added support for several new large SDRAM modules.
The program now identifies modules supporting the Athlon processor at CAS LATENCY 2. It will report the message "SPD=CL2 at 100MHz" in the last summary screen as well as in the Test Log.
Version 1.48 supports the new SIMCHECK 200-PIN DIMM adapter, p/n INN-8558-10. This adapter tests the DIMMs for SUN MICROSYSTEMS Sparc Station Servers. It also includes several new improvements in testing large SDRAM modules.
Version 1.47 provides an automatic detection of PC133 type modules. Please refer to the new application note INN-8558-APN18: DETERMINATION OF PC133 BY Sync DIMMCHECK 168.
Version 1.47 also includes an automatic kernel upgrade which will adjust the kernel portion of the FLASH in your SIMCHECK to version #3. After downloading this version and pressing Esc as prompted, you may notice a quick extra SECTOR FLASH message, during which the kernel is being upgraded. The Setup menu [F2 Setup- F3 Config-F4 More-F4 ProdInfo] will display the new kernel version. Kernel operation and features are generally transparent to most users and are important only for future hardware upgrades.
Version 1.46 supports the new SDRAM engine (HARDWARE VER.=2.02 in Setup Config More ProdInfo menu), as well as the existing Sync DIMMCHECK units. It also solves several reported bugs in testing large Registered SDRAM modules.
March Up/Down and the Auto-Loop routines have been improved with this version.
Version 1.45 improves the speed of Basic Test, particularly with larger SDRAM modules. It also support various enhancements to the newly released Version 2.02 of the SIMCHECK Communications PC program.
It also includes first support for Production Mode. Production Mode is a special mode of SIMCHECK operation in which the SPD chip of the tested module is automatically programmed at the conclusion of the test. For obvious reasons, Production Mode should be used only by Memory Manufacturers. Please review Application Note INN-8558-APN15: SIMCHECK II PRODUCTION MODE for further details before experimenting with the new program.
Version 1.44 fixes few reported bugs. We have added a module type indicator during SDRAM tests. The message "UBF" is used for UNBUFFERED and "REG" is used for REGISTERED modules. This indicator appears near the 3V marker at the right corner of the third display line. You can toggle this indicator OFF and ON (default) using the SETUP - CONFIG - SDRAM - REG/UBF.
This version provides first support for the new Sync DIMMCHECK 100. Testing of the 100-pin S.O. DIMM modules is similar to the other Sync DIMMCHECK tests.
It also incorporates initial implementation of 133MHz testing, in preparation for the next generation PC-133. Currently you can manually setup (through either change-on-the-fly or full setup) the test frequency to 133MHz, 125MHz, 112MHz or lower frequencies. When selecting a frequency in the range of 112MHz to133MHz, please note that the Full Page Burst, which is used to expedite the test during Basic Test, is automatically disabled. This should not diminish the test, since Intel's PC-100/66 standards do not require the full Page Burst option.
The change-on-the-fly feature for SDRAM tests now includes a quick means to toggle Fast Page Burst on or off.
You can now use F2 during Extensive test for EDO/FPM and SDRAM to jump back to a previous test phase.
This version includes first support for 168-pin Registered/Buffered SDRAM DIMMs. One or two Clocks with PLL devices are identified. It further supports the Sync CHIP Tester, a new optional SIMCHECK II adapter for testing individual SDRAM chips. We have also made further optimization in our SDRAM testing algorithm which results in a faster BASIC test using more patterns.
While most users should be able to use the unit at its default setup, Expanded SDRAM Configuration Setup now allows you to set wide margin for PC-100 or to disable the Full Page Burst tests. Use Setup-Configuration-More-Sdram to access the SDRAM Setup. Use F2 to select tight (default) or wide margin for PC-100 determination. Use F3 to disable the fast Full Page Burst so that some older modules may work on your SIMCHECK. The default state is to leave Full Page Burst on. The SDRAM configuration menu also includes the LOCK option (F1) which was released in version 1.35. This Lock option should be left at its default OFF state unless you are requested to activate it by our Tech. Support department.
This firmware is the first to support our new SIMCHECK II Communication Program for WIN95/98/NT.
This version includes the first deployment of the EXTENSIVE test phase for SDRAM DIMM modules. EXTENSIVE test for SDRAM modules follows similar test phases like our standard EDO/FPM EXTENSIVE TEST: Voltage Cycling, Mode Test, Voltage Bounce, March UP/DOWN, Chip Heat, and Final Test. Two test phases, Relative Refresh and Relative Spikes, are still undergoing some further development and will be implemented soon, but in a different way than our corresponding EDO/FPM tests.
The new SDRAM Mode Test check all the burst length options available on the tested module and reports as in the following examples:
"CL=3 BL=1+2+4+8+FULL" - meaning that at CAS Latency 3, Burst
Length of 1, 2, 4, 8 and FULL page were OK.
"CL=2 BL=1+2+4+8+FULL" - meaning that at CAS Latency 2, Burst
Length of 1, 2, 4, 8 and FULL page were OK.
"CL=3 BL=1+2+4+8" - indicates no support for FULL page burst length
"CL=2 BL=2+4+FULL" - indicates failures at CAS Latency 2 at burst length of 1 and 8.
The new Sync DIMMCHECK 144, our affordable 100MHz SDRAM/EDO/FPM 144-pin S.O. DIMM adapter for the SIMCHECK II product line, is now supported with this version. Testing of the 144-pin SDRAM S.O. DIMM modules is similar to the test of the 168-pin SDRAM DIMM modules.
We have added support for SDRAM devices that their burst length does not include the FULL PAGE option. Such modules are now identified with the message "NO FULL-PAGE BURST" in the test summary screen or in the Test Log. Please note that the FULL PAGE burst length is marked as OPTIONAL in the JEDEC standard and is NOT required by the Intel PC-100/66 standards.
We have also identified and corrected a problem with some modules during the entry into AUTO-LOOP.
The BASIC test for SDRAM testing has been completely revised as we have fully implemented our page burst mechanism. This will result with significantly higher coverage of memory errors during Basic Test. Accordingly, please review the online manual addendum for Sync DIMMCHECK, which has been completely revised for this version.
The page burst mechanism further enables the tester to determine if a module is within the PC-100 or PC-66 specification. For a detailed information regarding this new feature please review our latest application note INN-8558-APN14: DETERMINATION OF PC-100 BY Sync DIMMCHECK.
In previous versions, the program used the message "SPD=NOT FOR INTEL" whenever byte #126 of the SPD (Intel specification frequency) does not equal to either 64h or 66h. The new version replaces the previous message with the new message "SPD=JEDEC-NOT INTEL". If other bytes of the SPD do not conform to the general JEDEC standard, the program will notify you with the "SPD=NON-JEDEC" message.
The program can now test more SDRAM modules which do not support the Single Write function.
We have implemented new measurements for the Access Time From Clock to help determine if a module is within the PC-100 or PC-66 specification. This addition allows the Sync DIMMCHECK to automatically select 100MHz or lower speed operation based on the module actual timing parameters. For a detailed information regarding this important new feature please review our latest application note INN-8558-APN13: ACCESS TIMES FROM CLOCK MEASUREMENT BY Sync DIMMCHECK AND THE PC-100/PC-66 STANDARD.
We have also added the chip size information to both the Structure Summary Screen and the Test Log. It shows the size of each individual chip of the module, in the format of [number of banks] x [each chip bank's size in Meg] x [bus width in bits]. The following examples show some typical chip sizes:
2x1Mx8 - a 16Mbit chip with overall size of 2Mx8; 4x2Mx8 - a 64Mbit chips with overall size of 8Mx8; 4x4Mx4 - a 64Mbit chip with overall size of 16Mx4; 2x2Mx4 - a 16Mbit chip with overall size of 4Mx4; 4x1Mx16 - a 64Mbit chip with overall size of 4Mx16.
Release #2: 7-6-98 fixing a bug in testing the address lines of modules made of x16 bit chips. First release caused a wrong MA8 ERROR message.
We have implemented the Auto-Loop test for SDRAM modules so that our customers will be able to burn-in their modules and enjoy the benefits of more exhaustive tests of their modules. We are still developing the Extensive test for SDRAM and once it is available, Extensive test will follow Basic test in accordance with our normal test flow (Basic test > Extensive test >Auto Loop).
The Auto-Loop test for SDRAM is a bit different than our EDO/FPM Auto-Loop. In addition to changing the complex patterns, it also uses different functions to generate those patterns. Therefore, failure in Auto Loop will record the test function in the Test Log as AUTO-LOOP-A, AUTO-LOOP-B, etc. Also, you will notice that Loop #1 for example, may take longer to complete than Loop #5. The complex pattern tests show the first pattern of each pattern group on the first display line. You can disable the pattern display via Setup Configuration.
The Auto-Loop test also includes our new Self Refresh tests, which are initiated every 16 loops and may last 20 or 45 seconds each (these numbers are subject to change in upcoming versions). While a failure of an Auto-Loop complex pattern test terminates the tests with error messages and sounds, success or failure of the Auto-Loop Self Refresh tests are shown during the test as a transient 'OK' or 'FAIL' messages, and are recorded in the Test Log. For example, if all the Self Refresh tests during the Auto-Loop test are successful, the test end with a message 'SELF REFRESH OK' in the Test Log.
We have also added support for some more SDRAM DIMMs in this new version.
EDO/FPM mode test during Extensive test has been fully implemented. It now provides a measurement of the Tcac parameter - access time from CAS. The result of this test is also recorded in the test log.
Some early SIMCHECK II units cannot perform the mode test and will show a message "MUST UPGRADE SBPAL!". If you encounter this message during mode test, please contact your dealer for the upgrade SBPAL chip and the corresponding activation code. Since this SBPAL upgrade affect only the new mode test, you can continue to use your unit even before you perform this upgrade.
Change-on-the-fly has been redesigned to include refresh changes, and to provide better voltage control.
INNOVENTIONS' proprietary algorithm for automatic 3.3V / 5V detection is now fully implemented. In addition to the automatic detection, you can setup the voltage using the Voltage Setup or Change-on-the-fly features.
Setup Patterns have been implemented in Setup - Parameters - More - Patterns. It allows you to setup your own main (first two) 32-bit patterns for the Basic Test. These setup patterns default to 55555555h and AAAAAAAAh, and they are also used during Voltage Bounce and March Up/Down of the Extensive Test. Setup Patterns also controls the patterns for the SDRAM tests.
Refresh setup and refresh Change-on-the-fly are now available for the SDRAM tests.
Frequency setup is now available for the SDRAM tests.
We have corrected our clock number detection to reflect PC-100 modules with two clocks using CK0 and CK2 (rather than using CK0 and CK1 as per the JEDEC standard). The test program now reports 'CLOCKS: 2-Clk CK0+1' or '2-Clk CK0+2' in the log to distinguish between the two method of clock wirings.
Includes added support for modules using the popular 64Mb Hyundai chips.
Program now tests if the Single Write feature is available in the module and reports the result in the test log. Please note that the Single Write feature is not required by the INTEL PC-100 or PC-66, but is part of the JEDEC standard.
Test Log and the detailed Structure screens now show if the SPD claims compliance with Intel's PC-100 or PC-66. For example, if the SPD claims compliance with PC-100, you will see the message 'SPD=INTEL PC-100'. If the module has no SPD chip, you will see the message 'SPD MISSING'.
Customers using the Sync DIMMCHECK 168 with a SIMCHECK II se now have the ability to use the Change-On-The-Fly feature while testing SDRAM modules.
Several improvements have been implemented in the locking mechanism between SIMCHECK and the SyncDIMMCHECK. If you still experience inconsistent test results after upgrading to this version, there is an additional locking safeguard that you can enable from setup by selecting Setup-Config-SDRAM and toggling (F1) LOCK to ON (each time you press LOCK you toggle between ON or OFF). After exiting from setup, SIMCHECK automatically saves the new setup. Now whenever you turn SIMCHECK ON, the new locking mechanism checks the locking between SIMCHECK and the SyncDIMMCHECK, and if the locking is not optimal, you will notice one or more "LOCKING SDRAM..." messages.
Full support for SPD editing and programming. See SIMCHECK II SPD MANAGEMENT manual addendum for more details. SIMCHECK's SPD Management mode is where you read and write SPD data. When SIMCHECK operates as a stand alone unit, you can read SPD data from a master module into a buffer, and then use the buffer's data to verify or program SPD chips on other modules. When SIMCHECK communicates with the PC Downloader program (included with your SIMCHECK package, Version 1.07 can be upgraded from our Download page), you can further read SPD data into the PC, edit it, save it into *.spd files on your PC, or download stored SPD files into SIMCHECK buffer and then program other modules.
First release to support Sync DIMMCHECK 168. Please review the manual addendum for the Sync DIMMCHECK 168.
Added support for the Serial Presence Detect (SPD) for the DIMMCHECK 168P PRO and the DIMMCHECK 144 PRO.
1. Added support for the CHIP-HEAT mode, indicating the heating current in Ampere units.
2. Automatic translation of memory size from the 4Mx72 format to the 32M format at the end of BASIC and EXTENSIVE tests as well as in the Test Log.
A 32-bit version has been added to solve some compatibility issues with Windows NT. We now offer two zip files in our web site: "sim2d.zip" for Windows 3.1 (and Windows 95) or "sim2d32.zip" file for Windows NT (and Windows 95).
A downloader for SIMCHECK II se Activation Codes has been added.
1. Added support for the SIMCHECK II se.
1. Added support for the following 168-pin DIMMs: 66-bit SPARCstation 5 modules from SUN Microsystems, and 4Mx72DIMMs with Single -RAS line per bank from Acer.
2. Supporting the new 20-42 pin universal SOJ adapter for SIMCHECK II.
Improvement in the Test Log communication between SIMCHECK II and the PC. Test data is now immediately copied from SIMCHECK to the PC, without apparent latency.
Minor modification to avoid wrong SIMCHECK II's version indication at the Find SIMCHECK menu.
1. Single Bit Test is now available for all supported devices, including the 168-pin and 144-pin DIMMs.
2. Bits Error menu adds more detailed information messages. Press F4 to scroll down into these messages during the display of DATA BITS errors. Press F3 to scroll up.
3. More information has been added to the Test Log (and also to the PC Realtime Interface), including the additional error messages discussed above. Full structure information is now logged at the start of Basic Test, not at the end.
4. Please upgrade your PC programs: The SIMCHECK II Downloader should be upgraded to version 1.05, the Realtime interface should be upgraded to version 1.01.
5. Support for the new DIRECT PRINTER INTERFACE (p/n INN-8558-4). This option allows the user to connect SIMCHECK II directly to a printer to acquire hard copy reports of the SIMCHECK Test Log.
This is a maintenance upgrade with added support for several SIMM and DIMMs. In particular, the program now identifies three new ECC structures in 72-pin SIMM modules. These structures do not conform to the JEDEC ECC which dictates the use of single RAS/single CAS per bank and keeping PIN-48 at GND. Until (and if) these structures become JEDEC standard, the program identify them with the following temporary names:
"ECC=1-RAS" is close to the JEDEC standard where all data bits of bank0 are controlled by RAS0/CAS0, and the bits for bank1 are controlled by RAS1/CAS1.
"ECC=4-CAS" controls the parity bits on a single RAS (e.g. RAS2) with all 4 CAS lines. Data bits are controlled by the standard 2RAS/4CAS arrangement.
"ECC=CAS1" controls the parity bits by CAS1 only. Data bits are controlled by the standard 2RAS/4CAS arrangement. A type warning message appears when this module is tested since its wiring will not work in many "standard" motherboards.
1. Improved implementation of the MARCH algorithm in Extensive Test. The new March test should be useful in detecting interference between cells.
2. First support for INNOVENTIONS' Automatic SIMM/DIMM Handlers. This feature is activated in Setup, Config., More, Handler.
1. Test program now supports the new DIMMCHECK 144P PRO adapter (p/n INN-8558-2) which tests the 144-pin SO DIMMs.
2. New support for a group of x72 bit ECC mode 168-pin buffered DIMMs has been implemented. These type of ECC DIMMs are used, among others, on Compaq and IBM desktop computers. They are asymmetric in the sense that 40 bits are controlled by RAS0, CAS0, W0 and OE0 while the remaining 32 bits are controlled by RAS2, CAS4, W2 and OE2. SIMCHECK II identifies the following structures:
3. This version also corrects a bug that caused some high speed modules to show a wrong cycle time of 500nS.
1. Relative Refresh is now enabled. Results are shown in the scale of 0-9, similar to our SIMCHECK PLUS line.
2. Refresh Rate setup is now enabled for ADVANCED USERS. It can be reached at Setup (F2) -> Setup Parameters (F1) -> More (F4) -> Refresh (F2). You can set the refresh to Auto, None, or a fixed 2mS-999mS interval. Longer refresh intervals create slower refresh rate, and vice versa (refresh rate=1/refresh interval). Memory devices are better and typically consume lower power if they can sustain data at larger refresh intervals.
NOTES: Since the memory test typically covers all the rows in a rapid succession, the test itself actually refreshes the memory, even if you set refresh to None. Therefore, do not be surprise if most of your memory devices seem to work even when you set refresh to None or if you set it to a slow rate like 900mS. In such cases, you will notice failures mostly in large memory devices, during Auto-Loop. On the other hand, when setting refresh at an extremely fast rate, e.g. 4mS, large memory devices cannot be tested since the refresh activity takes most of the processor time. Therefore, our test program automatically increases your set refresh interval if it is found to be too fast for the tested memory. You can see the Actual refresh rate in the test log. For example, if you set refresh to 7mS and test a 4Mx32 device, you will see an actual refresh interval of 8mS. For 16M the minimum is 16mS, for 1M the minimum is 4mS. Our minimum values are well below the minimum specifications, thus allowing you to test the refresh capabilities of your memory.
1. First support for the SIMCHECK II Realtime Interface PC program.
2. A special graphic marker is now added to the LCD display to indicate 3.3V or 5V testing.
1. Support for the DIMMCHECK 168P PRO, the new universal adapter for 3.3V/5V buffered/unbuffered 168-pin DIMMs.
2. Support for the SIMCHECK II SIP ADAPTER.
3. Several previously unsupported modules are now automatically detected and supported.
1. Support for 30-pin and 72-pin SIMM modules with logic parity chips. This type of modules utilize logic chips to emulate real parity function. Since most current and new motherboards can be set for x32 bits, the popularity of such logic parity chips has been diminished recently. SIMCHECK II detects the parity logic, issues a device type warning and mark the tested device as either x8p or x32p.
2. Preliminary support for the new HP NETSERVER' s MANAGEABLE ECC modules. These modules are also called "EOS" for Ecc On a Simm" and they incorporate 48 bits and two special controller chips for each bank of 36 bits. Their unique technology actually corrects the errors on the module, thus making this module type the most reliable in the market. Currently our test is limited for BASIC TEST only.
3. Testflow setup has been significantly enhanced to allow more flexibility in creating customized test flow. You reach the Testflow Setup by pressing F2,F2 from Standby. Use Main Testflow (F1) to select "Basic Test -> End" or "Basic Test -> Auto Loop" or "Extensive Test -> Single Bit Test" or one of the other selections to alter the main test flow. Use Skip Test feature (F2) to skip individual tests.
1. Fixing a dynamic refresh problem in the Auto-Loop test algorithm for large size modules. Should fix reported problems where some 16Mx36 or similar modules would consistently fail during the Auto-Loop test.
2. Adding test voltage change on-the-fly (use F2 during basic test and select 5V or 3.3V testing). This feature works only when SIMCHECK II is in default voltage mode.
Minor corrections, particularly for 3.3V testing.
1. Test program now supports the DIMMCHECK 168P (both 5V and the 3.3V versions) adapters which test 168-pin DIMMs.
2. SIMCHECK II now supports the HP WORKSTATION 72-pin SIMM modules without the need of external adapter.
3. Old 2Mx8 30-pin SIMMs are now supported.
DRAM mode detection is now activated. Test program now identifies EDO (Extended Data Out), FPM (Fast Page Mode) modes, as well as the old NIBBLE mode. Extended wiring tests have been added to BASIC TEST. All wiring and mode errors are added to the stored Test Log.
The SINGLE BIT test is now fully integrated in the SIMCHECK II program. Please note that the description in the current Owner's Manual (printed 8-28-96) is no longer valid. Please print the information below and insert it following page 32 of your manual.
Access to the SINGLE BIT test has been significantly improved over SIMCHECK I. You can reach the SINGLE BIT test by pressing F3 from BASIC test, EXTENSIVE test, and AUTO-LOOP. If an error was found by BASIC test, you may still go to SINGLE BIT test from STANDBY during the first 3 seconds, or so, after returning to STANDBY from the error.
SINGLE BIT test has two views: the GRAPH view and the BIT view. The GRAPH view shows the status of all the bytes of the module, with a local zoom on the currently tested bit. It is similar to SIMCHECK I and is the default viewer. The BIT view concentrates only on the currently tested bit, showing the exact -CASx and -RASx control lines which are needed to activate it. The BIT view also identifies the tested bit's pin number and its JEDEC's 'DQ' name. You can toggle between the two views at any time during the SINGLE BIT TEST by pressing F1.
F2-F5 function the same regardless of the selected view. F2 (left <- ) allows you to skip left to the previous bit. F5 (right -> ) allows you to skip right to the next bit. F3 restarts the SINGLE BIT test, and F4 is the HALT button. You can halt the test at any time and use F2 or F5 to scan previous results during the halt mode. Press F4 again to continue the test at the current bit setting. A special progress counter is placed on the top right corner. It shows two numbers, like 23/72. The right number is the number of bits times the number of banks which equals to the total of all the individual bits to test. The left number shows how many individual bits have been tested. If you use F5 to skip several bits, you will see that the left number will not reach 72 until all skipped bits are tested! Once you reach a full test (72/72 or 32/32 or 9/9 etc.) the left number increments at every subsequent bit test.
1. The new Test Log feature can be accessed from STANDBY mode by pressing F4. If you have a customized setup, there will be a menu to select VIEW SETUP or VIEW TEST LOG. If SIMCHECK II is left in its AUTO/DEFAULT SETUP, you reach the Test Log directly. Upon power on, the Test Log is empty. After each test, the Test Log keeps all the test results in great details until you start testing your next device. Error reports (if any) are automatically revisited at the end of the Test Log. If you have multiple error reports stored in the test log, you may press F1 to exit each error menu, then press Esc to go back to STANDBY mode.
2. Relative Spikes test is now enabled.
To contact our Tech Support: Call (281) 879-6226 M-F 9:00-5:00 Central Time, or send your E-mail to support@innoventions.com.
Product operation and specifications are subject to change without prior notice.
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