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RAMCHECK APPLICATION NOTE INN-8668-APN5
INN-8668-APN5
--Created: 6-26-02 (first published for RAMCEHCK)
--Last Updated: 1-07-19
This Application Note discusses the complexity of memory test algorithms and their impact on overall test accuracy. We discuss the implication of this complexity on the RAMCHECK LX test results.
The RAMCHECK LX (and its predecessors, the RAMCHECK and the SIMCHECK II) proprietary test algorithms were developed for optimum efficiency and fast testing. The memory tester utilizes different patterns and different algorithm during the various test phases. Memory tests are generally of type O(n), using MARCH, CHECKER, (partial) WALKING 0s, (partial) WALKING 1s and Surround Disturb Patterns.
The inherent complexity of testing a memory chip can be understood from the following example: Let us assume that we want to test a simple hypothetical memory chip of only 8 cells (bits). A simple approach is to first write "0" in all the cells and verify that the cells hold the data, and then write "1" in all the cells and verify these eight "1"s. Thus in only 16 write/read cycles we have "completely checked" this chip. However, there is a major flaw in this conclusion since it is possible that cell number 2 is shorting (or otherwise disturbing) cell 7, and the above test will not detect this short because the cells are both written "0" or "1" at the same time. A short between a pair of bits can be detected only when each bit stores opposite values.
An alternate approach is to exhaustively test the memory with all possible combinations of "0"s and "1"s in all the cells. First we write and verify with all "0"s. Second, we write and verify with "1" in cell 1 and "0"s in all other cells. The third test checks cell 2 with "1", "0"s in all others, etc. This way all the combinations of "1"s and "0"s are generated to detect all the possible shorts. Overall, we need to test this hypothetical chip with 28=256 patterns. Based on the example above, it will take at least 2256,000 accesses to fully test even a tiny old 256Kb memory chip. Similarly, it will take 2256,000,000 or 21,024,000,000 to exhaustively test today's 256Mb or 1Gb memory chips. These numbers are astronomical, and therefore it is theoretically impossible to create a tester for a modern memory chip with 100% accuracy. Various algorithms like GALPAT have been developed which require order of O(n2) tests, where n is the total number of bits. While such algorithm can reach close to 100% accuracy, they take unreasonably long time. For example, today's 256,000,000 bit memory will require k*256,000,000*256,000,000 tests (k is an implementation dependent constant). Assuming k to be 6 for a typical application, this algorithm takes at least million of hours to complete at current memory access times. Obviously, no tester can be sold and used if it takes hundereds of years to test one 256Mb chip.
Fortunately, most inter-cell disturbances in a memory chip tend to occur between adjacent cells, so that a fully exhaustive test as mentioned above is not required. Over the years, a variety of approximate tests that try to cover most inter-cell disturbances were developed. At the minimum, the disturbances can be tested only for the immediate four neighbors of each cells. More advanced tests look at more adjacent cells, at the cost of a much longer test time
The advanced tests which are done by a certifying memory tester (a rack mount system costing above $500,000) are in fact based on adjacent cell topography.
Such tests must be custom-written for each individual memory die and take into account the exact placement of each memory cell inside the internal memory array. Since even a full adjacent interference test may take hours, a certifying memory tester will first run very long tests on a representative sample of memory chips from a production batch, and then the test is significantly shortened to cover only those critical areas which were found to be sensitive on the samples. The resulting optimized tests are then used for testing all the remainder of the memory chips from the same production batch.
A full certifying test program written for one specific chip will not have the same fault detection coverage when testing a different chip with the same size and structure. In fact, when a manufacturer changes the version of the die of the same memory chip, the optimized test program must be modified. Because of this custom programming complexity and high equipment cost, such certifying memory testers are used only by the prime memory manufacturers and by companies with extremely critical missions.
Since memory devices exhibit reduced capabilities at higher temperature, many certifying memory testers must also employ a special environment chamber to heat the memory devices up to 70 degrees Celsius. And yet, even with heat chambers, the advanced electronics, and the customized programming, the certifying memory testers are still unable to provide 100% exhaustive coverage!
Modern DDR4 and DDR3 memory must meet a very long list of timing and voltage parameters, as defined in the relevant JEDEC standards. This makes fully parametric testers extremely expensive and complex - they need to control delicate timing and analog level (current, voltage) parameters on every pin connected to the memory device under test. RAMCHECK LX is not such a fully parametric tester that can be used to certify memory modules.
INNOVENTIONS developed the world's first portable memory tester in the mid-1980's, and since then, our test algorithms have been continuously improved to achieve unparalleled accuracy in testing memory chips. But obviously, we cannot compare our low-cost functional memory testers with the certifying memory testers that cost $500,000 or above. And we are definitely the last to claim that our testers can detect 100% of all memory faults!
RAMCHECK LX is a functional tester that is easy to use and provides fast test results. There is no need for setup or required programming - the tester identifies the memory structure and runs optimized algorithms that we have developed over the last 30 years. We have incorporated advanced electronic components in our design. For example, using programmable voltage sources, our test algorithms use advanced tests incorporating Voltage Bounce and Voltage Cycling. The first provides higher accuracy in detecting pattern sensitivity and other intermittent memory problems. The latter provides additional assurance of proper product operation under the entire manufacturer's voltage specifications. In many cases, our high speed phasing and timing devices allow our testers to determine timing related problems. Another addition is our Chip-Heat mode, which warms the tested module to working temperatures (but not to the maximum 70 degrees Celsius of the heat chambers), thereby improving the reliability of temperature related measurements.
Even with the many complexities associated with memory testing, we firmly stand behind our testers. Their success over the years indicates that they are an indispensable reference tools capable of detecting most defective memory modules.
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